Schematic Capture for ALU Design: CDA 4203L Lab 1 Tutorial

Introduction to Schematic Capture for ALU Design

In CDA 4203L Spring 2025, Lab 1 challenges you to implement an Arithmetic Logic Unit (ALU) using schematic capture in Xilinx ISE. This tutorial guides you through the design process, from understanding the requirements to simulating your circuit. We'll use timely examples, like how a modern AI accelerator's ALU handles multiple operations, to illustrate concepts.

Understanding the ALU Requirements

Your ALU must support four functions: invert all bits of A, add A + B, subtract A - B, and double A (2*A). The inputs are 4-bit signed numbers in two's complement. The output Y is also 4-bit. You must discard the end-round carry and avoid overflow cases (e.g., adding two positives that exceed +7). Think of this like a gaming console's math coprocessor that must handle scores correctly without overflow.

Function Table and Operation

The function select lines S1 and S0 choose the operation:

00: Invert all bits of A (bitwise NOT)
01: Add A + B
10: Subtract A - B
11: Double A (2*A)

For subtraction, you'll use two's complement addition (A + (~B) + 1). For doubling, a left shift with overflow detection is needed.

Designing the ALU Hierarchically

Start with the schematic capture tutorial (Tutorial_Lab1.pdf). Then, create a hierarchical design: a top-level ALU block that instantiates sub-blocks like a 4-bit adder/subtractor, a bitwise inverter, a shifter, and a 4-to-1 multiplexer. This modular approach is similar to how modern AI chips are designed using reusable IP cores.

Step 1: Create the Full Adder (1-bit)

Build a 1-bit full adder using gates (AND, OR, XOR). This will be used in the 4-bit adder. Use the ISE schematic editor to place symbols and wire them. Test each block individually.

Step 2: Build the 4-bit Adder/Subtractor

Connect four full adders in ripple-carry fashion. For subtraction, XOR each B bit with the control signal (Add/Sub) and set the carry-in to 1. This is a classic design, like the core of a CPU's ALU.

Step 3: Implement the Inverter and Doubler

The inverter is simply NOT gates on each A bit. The doubler (2*A) is a left shift by one bit, with overflow detection: if the two most significant bits differ, overflow occurs. For simplicity, you can implement it as a separate block using a shifter and overflow logic.

Step 4: Create the 4-to-1 Multiplexer

Use a 4-bit wide 4-to-1 MUX to select the output from the four function blocks. The select lines S1 and S0 drive the MUX. This is similar to how a smartphone's GPU selects different rendering modes.

Test Bench and Simulation

Create a test bench (VHDL or Verilog) that applies test vectors for each function. Include at least two vectors per function, covering normal cases and overflow-avoided cases. For example:

Invert: A=1101 (invert to 0010)
Add: A=0110 (+6) + B=0001 (+1) = 0111 (+7); A=1111 (-1) + B=0111 (+7) = 0110 (+6)
Subtract: A=1111 (-1) - B=1110 (-2) = 0001 (+1); avoid overflow like A=0001 (+1) - B=1000 (-8)
Double: A=0011 (+3) gives 0110 (+6); A=0100 (+4) gives 1000 (-8, overflow)

Run simulation in ISim and capture waveforms. Label each test case. This process is akin to testing a new AI model's math accuracy.

Report Organization

Your report must include: a cover sheet, top-level and all sub-block schematics (screenshots), a brief design description, simulation waveforms with annotations, and feedback (hours spent, difficulty). Use the provided template.

Common Pitfalls and Tips

Overflow: Remember to discard the end-round carry. Use overflow detection for add/subtract by checking if the sign of inputs and output differ.
Two's complement: Ensure you understand that the MSB is the sign.
Hierarchy: Keep your design hierarchical for easier debugging.
Simulation: Use a test bench that cycles through all functions and inputs.

Conclusion

By following this guide, you'll master schematic capture for ALU design. This lab builds foundational skills for computer architecture, applicable to modern processors and AI accelerators. Good luck!