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Digital Signal Processing on DE1-SoC: Audio CODEC and Tone Generation Tutorial

Learn how to use the audio CODEC on the DE1-SoC board to pass audio through FPGA, generate tones from memory, and filter noise. Step-by-step guide with code examples.

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Introduction to Digital Signal Processing with DE1-SoC

Digital Signal Processing (DSP) is at the heart of modern audio applications, from noise-canceling headphones to AI-powered voice assistants. In this tutorial, you will explore the audio CODEC on the DE1-SoC board, a popular FPGA platform used in university labs like EE371. By understanding how to sample, store, and playback audio, you'll build a foundation for more advanced DSP projects. Whether you're working on a lab assignment or a personal project, mastering the CODEC interface is essential.

Understanding the Audio CODEC Interface

The DE1-SoC board includes an audio CODEC that samples sound at 48 kHz, providing 24-bit stereo data. The system uses a clock generator, an Audio CODEC Interface, and an Audio/Video Configuration module. The key signals are read_ready, write_ready, read_data, write_data, and read_en/write_en. The CODEC stores samples in a 128-element buffer. When read_ready is high, you can assert read_en to get the next sample. Similarly, assert write_en when write_ready is high to send a sample to the output.

Task 1: Passing Audio Through the FPGA

In this task, you'll create a simple pass-through circuit that routes audio from the microphone input to the speaker output. The challenge is to synchronize the read and write operations. You must wait until both read_ready and write_ready are high before transferring data. Below is a Verilog snippet for the control logic:

always @(posedge clk) begin
    if (reset) begin
        read_en <= 0;
        write_en <= 0;
    end else begin
        if (read_ready && write_ready) begin
            read_en <= 1;
            write_en <= 1;
        end else begin
            read_en <= 0;
            write_en <= 0;
        end
    end
end

assign write_data = read_data;

After compiling and uploading to the DE1-SoC (or using LabsLand), you can test by playing an audio file into the microphone and recording the output. This pass-through is the foundation for more complex DSP algorithms like filtering.

Task 2: Generating a Tone from Memory

To generate a tone, you need to store a waveform in ROM and output it at the sample rate. First, use the provided Python script to create a MIF file for a sine wave at a desired frequency (e.g., 440 Hz). The script calculates the samples for one period and writes them to a MIF file. Then, in Quartus, create a ROM megafunction initialized with that MIF file. The ROM should have 24-bit words and the number of words equal to the length of your waveform.

Next, design a counter that increments the ROM address each time you write a sample to the CODEC. When the counter reaches the end, it wraps around. Here's an example:

reg [9:0] addr;
wire [23:0] rom_data;

rom sine_rom (
    .address(addr),
    .clock(clk),
    .q(rom_data)
);

always @(posedge clk) begin
    if (reset) begin
        addr <= 0;
    end else if (write_ready && write_en) begin
        if (addr == 999) // assuming 1000 samples
            addr <= 0;
        else
            addr <= addr + 1;
    end
end

assign write_data = rom_data;

Compile and test. You should hear a continuous tone from the speakers. This technique is used in synthesizers and game audio engines.

Connecting DSP to Current Trends

DSP is everywhere. For example, AI-powered noise cancellation in earbuds uses adaptive filters to remove background sounds. In gaming, real-time audio processing creates immersive environments. Even in finance, DSP algorithms analyze market data as time-series signals. Understanding how to manipulate audio on an FPGA gives you a hands-on edge in these fields.

Best Practices and Common Pitfalls

  • Always check ready signals: Ignoring them leads to data loss or glitches.
  • Use the correct clock domain: The CODEC interface runs on the 50 MHz clock, but the audio data is asynchronous.
  • Test incrementally: Start with pass-through, then move to tone generation.
  • LabsLand specifics: Upload your audio file alongside the compiled circuit. Record the output to verify.

Conclusion

You've learned the basics of digital signal processing on the DE1-SoC: passing audio through the FPGA and generating a tone from memory. These skills are directly applicable to your EE371 lab and beyond. Experiment with different waveforms, frequencies, and even implement a simple low-pass filter. The world of DSP is yours to explore.